I. Field of the Invention
The present invention relates generally to dynamic random access memory (DRAM). More specifically, the present invention relates to an improved memory device, which permits increased memory size with reduced power requirements.
II. Description of the Related Art
Improved manufacturing techniques are constantly being developed to increase the memory capacity of DRAM. These techniques have increased the possible number of transistors and other components on a single silicon chip. However, with increased capacity, the need for reduced power requirements still exists. This is most readily apparent in mobile devices which utilize memory, e.g., laptop computers, cellular telephones, etc.
New DRAM device bus architectures have also increased the speed of DRAM access. However, this increased speed results in greater power consumption and heat generation, which may cause overheating problems. For example, a Rambus DRAM SIMM (single in-line memory module) typically contains a heat sink as an effort to address the overheating problem. Therefore, a DRAM architecture that reduces power consumption would also help alleviate overheating associated with these new faster DRAM devices. Accordingly, there is a need for a memory device having increased memory size, yet reduced power consumption.
The present invention provides a device and method that permits the use of modern techniques to increase DRAM memory size while reducing power consumption. The present invention utilizes the internal memory sub array partitioning of a DRAM device and provides the capability of independently powering down each internal memory sub array thereby reducing power consumption when memory sub arrays are not being used for a period of time.